1. Field of the Invention
The invention relates to a memory controller, and more particularly, to a memory controller with a clock duty cycle adjusting mechanism.
2. Description of the Related Art
When a dynamic random access memory (DRAM) controller accesses a DRAM, the DRAM controller transmits a clock signal to the DRAM and the DRAM sends back a DQS signal to the DRAM controller for sampling the data signal DQ. The sampling signal DQS is generated based on the clock signal and if the quality of the clock signal, such as the duty cycle, is not good enough, the data acquired by the DRAM controller may be faulty.
FIG. 1 is a timing diagram showing a DDR DRAM read operation with a balanced clock duty cycle. In FIG. 1, the duty cycle of the clock signal transmitted to the DRAM is 50%, such that the signal DQS is driven by the clock signal with a duty cycle of 50%. Accordingly, an optimal timing margin is achieved.
FIG. 2 is a timing diagram showing a DDR DRAM read operation with an unbalanced clock duty cycle. In this example, the duty cycle of the clock signal transmitted to the DRAM is smaller than 50%, such that the signal DQS is driven by the clock signal with a duty cycle of less than 50%. Accordingly, the DRAM controller may not acquire the correct signal DQ and an optimal timing margin is not achieved. Note that the timing margin of the signal DQ varies according to the magnitude of the duty cycle, and if the timing margin is smaller than a predetermined value, such at those found at parts A and C of FIG. 2, the DRAM controller may not acquire correct data.